US 12,222,617 B2
Array substrate and display apparatus
Jianhua Huang, Beijing (CN); Chongyang Zhao, Beijing (CN); Zhihua Sun, Beijing (CN); Yingmeng Miao, Beijing (CN); and Yingying Qu, Beijing (CN)
Assigned to BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/441,304
Filed by BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Feb. 2, 2021, PCT No. PCT/CN2021/074940
§ 371(c)(1), (2) Date Sep. 21, 2021,
PCT Pub. No. WO2021/190159, PCT Pub. Date Sep. 30, 2021.
Claims priority of application No. 202010213325.3 (CN), filed on Mar. 24, 2020.
Prior Publication US 2022/0317530 A1, Oct. 6, 2022
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1368 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/1368 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An array substrate, having a display area and a peripheral wiring area provided at at least one side of the display area, wherein the array substrate comprises a base substrate, and the display area comprises a thin film transistor and a common electrode formed on the base substrate; the peripheral wiring area comprises a first lead, a gate signal line and a common signal line formed on the base substrate;
the thin film transistor comprises a gate electrode, and the first lead and the gate electrode are arranged in an identical layer and are electrically connected;
the gate signal line is located on a side of the first lead away from the base substrate, and is electrically connected to the first lead through a first transfer structure;
the common signal line is located on a side of the first lead away from the base substrate and located on a side of the gate signal line close to the display area, and the common signal line is electrically connected to the common electrode,
wherein, the first transfer structure is located on a side of the common signal line away from the display area,
wherein the peripheral wiring area further comprises a second lead formed on the base substrate, and the second lead is provided on an identical layer with the gate electrode and is electrically connected to the common electrode;
the common signal line is electrically connected to the second lead through a second transfer structure,
wherein the second transfer structure is closer to the display area than the first transfer structure,
wherein the second transfer structure comprises:
at least one third via hole, wherein an orthographic projection of the third via hole on the base substrate is located within an orthographic projection of the common signal line on the base substrate, and the third via hole exposes at least a part of the common signal line;
at least one fourth via hole, wherein an orthographic projection of the fourth via hole on the base substrate is located within an orthographic projection of the second lead on the base substrate, and the fourth via hole exposes at least a part of the second lead;
a second transfer portion, located on a side of the common signal line away from the base substrate, wherein the second transfer portion is electrically connected to the common signal line through the third via hole, and is electrically connected to the second lead through the fourth via hole.