US 12,222,545 B2
Package and method of forming same
Chih-Hsuan Tai, Taipei (TW); Chung-Ming Weng, Hsinchu (TW); Hung-Yi Kuo, Taipei (TW); Cheng-Chieh Hsieh, Tainan (TW); Hao-Yi Tsai, Hsinchu (TW); Chung-Shi Liu, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 18, 2023, as Appl. No. 18/302,046.
Application 18/302,046 is a division of application No. 16/884,843, filed on May 27, 2020, granted, now 11,635,566.
Claims priority of provisional application 62/941,229, filed on Nov. 27, 2019.
Prior Publication US 2023/0266528 A1, Aug. 24, 2023
Int. Cl. G02B 6/13 (2006.01); G02B 6/12 (2006.01); G02B 6/30 (2006.01); G02B 6/42 (2006.01); G02B 6/43 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/492 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01); H01L 23/31 (2006.01)
CPC G02B 6/13 (2013.01) [G02B 6/12002 (2013.01); G02B 6/12004 (2013.01); G02B 6/30 (2013.01); G02B 6/4214 (2013.01); G02B 6/424 (2013.01); G02B 6/4249 (2013.01); G02B 6/43 (2013.01); H01L 21/56 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/167 (2013.01); G02B 2006/12147 (2013.01); G02B 6/4232 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2221/68331 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2223/6627 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/214 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2924/10156 (2013.01); H01L 2924/10157 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1815 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
attaching a photonic integrated circuit die to a carrier substrate, the photonic integrated circuit die comprising an optical coupler and an insulting layer over the optical coupler;
forming a first opening through the insulating layer;
forming an encapsulant over the carrier substrate and the photonic integrated circuit die, the encapsulant extending along a sidewall of the photonic integrated circuit die;
after forming the encapsulant, forming a first redistribution structure over the photonic integrated circuit die and the encapsulant, wherein forming the first redistribution structure comprises:
forming a first dielectric layer over the encapsulant and the photonic integrated circuit die; and
after forming the first dielectric layer, forming a conductive line over the first dielectric layer, the conductive line extending through the first dielectric layer; and
after forming the first redistribution structure, patterning the first redistribution structure to form a second opening in the first redistribution structure, the second opening extending through the first opening in the insulating layer and exposing the optical coupler.