| CPC G01R 19/10 (2013.01) [H03K 17/56 (2013.01)] | 12 Claims |

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1. A method comprising:
switching a first transistor on and off in accordance with a logic signal, with a load current passing through the first transistor while it is switched on;
providing a sense current that is indicative of the load current via a second transistor that is coupled to the first transistor such that the first and the second transistors are switched on and off simultaneously;
determining an end of a switch-on phase of the second transistor; and
providing a current sense signal that represents the sense current between a first time instant, which corresponds to the determined end of the switch-on phase, and a second time instant, at which the logic signal signals a switch-off of the first transistor.
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