US 12,222,376 B2
Peak voltage detection circuit with reduced charge loss
Indranil Som, West Bengal (IN); Vaibhav Anantrai Ruparelia, Bengaluru (IN); and Kuppireddy Vasudeva Reddy, Bangalore (IN)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Jul. 29, 2022, as Appl. No. 17/815,961.
Prior Publication US 2024/0036087 A1, Feb. 1, 2024
Int. Cl. G01R 19/04 (2006.01)
CPC G01R 19/04 (2013.01) 20 Claims
OG exemplary drawing
 
8. A circuit structure comprising:
a peak voltage detector coupling a first input node and a second input node to an output node, wherein the peak voltage detector includes,
a first operational transconductance amplifier coupling the first input node and the second input node to an amplifier output node,
a first transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the amplifier output node to a supply voltage, and
a second transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the supply voltage to the output node of the peak voltage detector;
an input line coupled to the first input node of the peak voltage detector;
a first electrically actuated switch coupled to the second input node of the peak voltage detector; and
a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor,
wherein the first electrically actuated switch and the second electrically actuated switch each include a respective control node coupled to the input line, such that a signal in the input line enables current flow through the first electrically actuated switch and the second electrically actuated switch.