US RE50,290 E1
Shift register, driving method thereof, gate driving circuit, and display device
Xuehuan Feng, Beijing (CN); and Yongqian Li, Beijing (CN)
Assigned to HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/889,180
Filed by HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jan. 9, 2019, PCT No. PCT/CN2019/070966
§ 371(c)(1), (2) Date Mar. 9, 2020,
PCT Pub. No. WO2020/142923, PCT Pub. Date Jul. 16, 2020.
Application 17/889,180 is a reissue of application No. 16/645,733, filed on Jan. 9, 2019, granted, now 11,302,257, issued on Apr. 12, 2022.
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3258 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3258 (2013.01); G11C 19/28 (2013.01); G11C 19/287 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A shift register comprising a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit;
wherein the blanking input circuit is configured to provide a blanking input signal from a blanking input signal terminal to a first control node according to a second clock signal from a second clock signal terminal; [ node, wherein the blanking input circuit comprises a first transistor; wherein a first electrode of the first transistor is coupled to the blanking input signal terminal, and wherein a second electrode of the first transistor is coupled to the first control node; ]
wherein the blanking control circuit is configured to provide a first clock signal from a first clock signal terminal to a second control node and maintain a voltage difference between the first control node and the second control node, according to a voltage of the first control node [ comprises a second transistor, wherein a control electrode of the second transistor is coupled to the first control node, and wherein a second electrode of the second transistor is coupled to the second control node] ;
wherein the blanking pull-down circuit is configured to provide a voltage of the second control node to a pull-down node according to the [ a ] first clock signal [ , wherein the blanking pull-down circuit comprises a third transistor and a third leakage-preventive transistor; wherein a control electrode of the third transistor is coupled to a first clock signal terminal, wherein a first electrode of the third transistor is coupled to the second control node, and wherein a second electrode of the third transistor is coupled to a first electrode of the third leakage-preventive transistor; a control electrode of the third leakage-preventive transistor is coupled to the first clock signal terminal; and a second electrode of the third leakage-preventive transistor is coupled to the pull-down node] ; and
wherein the shift register circuit is configured to provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal according to a voltage of the pull-down node [ ; and
wherein the shift register circuit further comprises a twenty-ninth transistor, wherein a control electrode of the twenty-ninth transistor is coupled to the pull-down node, a first electrode of the twenty-ninth transistor is coupled to a first voltage terminal, and a second electrode of the twenty-ninth transistor is coupled to the second electrode of the third transistor] .