US 12,219,883 B2
Techniques for forming self-aligned memory structures
Stephen W. Russell, Boise, ID (US); Andrea Redaelli, Calolziocorte (IT); Innocenzo Tortorelli, Cernusco sul Naviglio (IT); Agostino Pirovano, Milan (IT); Fabio Pellizzer, Boise, ID (US); and Lorenzo Fratin, Buccinasco (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 4, 2022, as Appl. No. 17/881,274.
Application 17/881,274 is a continuation of application No. 16/539,932, filed on Aug. 13, 2019, granted, now 11,417,841.
Prior Publication US 2023/0027799 A1, Jan. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/066 (2023.02) [H10B 63/84 (2023.02); H10N 70/063 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a set of first sections of a layered assembly of materials comprising a layer of first placeholder material, a layer of electrode material, and a layer of conductive material above a substrate, each first section extending in a first direction;
forming a set of first insulative sections, each first insulative section disposed between a respective pair of first sections of the set of first sections;
forming a second placeholder material above the set of first sections and the set of first insulative sections;
forming a set of second sections extending in a second direction, each second section comprising the second placeholder material;
forming a set of second insulative sections, each second insulative section disposed between a respective pair of second sections of the set of second sections, wherein each second section of the respective pair of second sections includes the second placeholder material when the set of second insulative sections are formed;
forming a set of cavities, each cavity exposing an upper surface of the electrode material and exposing at least a portion of a respective sidewall of a first insulative section of the set of first insulative sections and a portion of a respective sidewall of a second insulative section of the set of second insulative sections; and
depositing a memory material in each cavity of the set of cavities such that the memory material is in direct contact with an edge portion of the upper surface of the electrode material, wherein the edge portion abuts the respective sidewall of the first insulative section and the respective sidewall of the second insulative section, wherein the memory material in each cavity is deposited adjacent to the respective sidewall of the first insulative section and adjacent to the respective sidewall of the second insulative section.