| CPC H10N 50/80 (2023.02) [H10B 61/22 (2023.02); H10N 50/01 (2023.02)] | 20 Claims |

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12. A manufacturing method of a memory device, comprising:
forming a bottom electrode material layer, a magnetic tunnel junction (MTJ) material layer, and a top electrode layer;
patterning the bottom electrode material layer, the MTJ material layer, and the top electrode layer to respectively form a bottom electrode, a memory material stack that comprises a magnetic tunnel junction which includes a free layer, and a top electrode;
forming an etch stop layer and a dielectric layer over the top electrode; and
forming a conductive contact structure through the dielectric layer and the etch stop layer, wherein the conductive contact structure comprises:
a metallic fill material;
a bottom surface that is formed directly on a top surface of the free layer; and
a top surface which is formed within a same horizontal plane as a top surface of the dielectric layer, said bottom surface being a bottom surface of said metallic fill material, and said top surface of the conductive contact structure being a top surface of said metallic fill material,
wherein the conductive contact structure comprises an upper portion having a first sidewall and a lower portion having a second sidewall, and wherein a top periphery of the second sidewall is laterally offset inward relative to a bottom periphery of the first sidewall by a connecting surface segment such that a vertical cross-sectional view of the conductive contact structure has a stepped vertical cross-sectional profile in which a width of the conductive contact via structure increases stepwise along a vertical direction at the connecting surface segment.
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