| CPC H10N 50/10 (2023.02) [H10B 61/20 (2023.02); H10N 50/80 (2023.02)] | 18 Claims |

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1. A semiconductor device comprising:
a magnetic tunnel junction stack comprising a bottom electrode, magnetic tunnel junction layers upon the bottom electrode, and a top electrode upon the magnetic tunnel junction layers;
a dual layer contact upon the magnetic tunnel junction stack, the dual layer contact comprising a conductive lower contact in physical contact with the top electrode and a conductive upper contact in physical contact with at least a portion of a top surface of the conductive lower contact, wherein the conductive lower contact is wider than the conductive upper contact; and
a first interlayer dielectric (ILD) in physical contact with an outer sidewall of the conductive lower contact and in physical contact with a bottom surface of the conductive lower contact, wherein the top surface of the conductive lower contact is coplanar with a top surface of the first ILD.
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