US 12,219,851 B2
Array substrate, fabricating method therefor and display panel
Li Liu, Beijing (CN); Pengcheng Lu, Beijing (CN); Rongrong Shi, Beijing (CN); Yuanlan Tian, Beijing (CN); Junbo Wei, Beijing (CN); and Dacheng Zhang, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
Filed on May 22, 2023, as Appl. No. 18/321,657.
Application 18/321,657 is a continuation of application No. 17/259,729, granted, now 11,758,786, previously published as PCT/CN2020/079876, filed on Mar. 18, 2020.
Prior Publication US 2023/0301152 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10K 59/35 (2023.01); H10K 50/818 (2023.01); H10K 50/852 (2023.01); H10K 50/856 (2023.01); H10K 59/123 (2023.01); H10K 71/00 (2023.01); H10K 102/10 (2023.01)
CPC H10K 59/353 (2023.02) [H10K 50/818 (2023.02); H10K 50/852 (2023.02); H10K 50/856 (2023.02); H10K 59/123 (2023.02); H10K 71/00 (2023.02); H10K 2102/102 (2023.02); H10K 2102/103 (2023.02)] 15 Claims
OG exemplary drawing
 
1. An array substrate, comprising a driving circuit board, and a first electrode layer, an insulating layer, and an anode structure sequentially stacked on the driving circuit board; the anode structure comprising a reflective layer, an intermediate dielectric layer, and a transparent conductive layer sequentially provided in a direction away from the driving circuit board, wherein
the array substrate has a first pixel region, a second pixel region, and a third pixel region;
the anode structure comprises a first anode structure in the first pixel region, a second anode structure in the second pixel region, and a third anode structure in the third pixel region;
the first electrode layer comprises a first sub-portion in the first pixel region, a second sub-portion in the second pixel region, and a third sub-portion in the third pixel region; the first anode structure is coupled with the first sub-portion through a first via hole provided in the insulating layer, the second anode structure is coupled with the second sub-portion through a second via hole provided in the insulating layer, and the third anode structure is coupled with the third sub-portion through a third via hole provided in the insulating layer;
an orthographic projection of the first via hole on the driving circuit board is located outside an orthographic projection of the intermediate dielectric layer on the driving circuit board, and an uppermost end of the first via hole is in contact with a lowermost surface of the transparent conductive layer in the first anode structure;
an orthographic projection of the second via hole on the driving circuit board is located outside the orthographic projection of the intermediate dielectric layer on the driving circuit board, and an uppermost end of the second via hole is in contact with a lowermost surface of the transparent conductive layer in the second anode structure; and
an orthographic projection of the third via hole on the driving circuit board is located outside the orthographic projection of the intermediate dielectric layer on the driving circuit board, and an uppermost end of the third via hole is in contact with a lowermost surface of the transparent conductive layer in third anode structure.