a plurality of gate lines respectively extending along a first direction;

a plurality of data lines respectively extending along a second direction;

a plurality of voltage supply lines respectively extending along the second direction; and

a pixel driving circuit;

wherein the pixel driving circuit comprises a driving transistor; a first transistor; a second transistor; a third transistor, and a storage capacitor; and

the storage capacitor comprises a first capacitor electrode and a second capacitor electrode;

wherein the array substrate comprises:

a semiconductor material layer on a base substrate;

an interference preventing block on the base substrate, the interference preventing block comprising a first arm and a second arm;

a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to the first capacitor electrode through a first via, and connected to the semiconductor material layer through a second via; and

wherein, along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by the first arm, and is spaced apart from a second adjacent data line by the second arm; and

an orthographic projection of the respective one of the plurality of voltage supply lines on the base substrate substantially covers at least 30% of an orthographic projection of the second arm on the base substrate.