US 12,219,813 B2
Light emitting element display device
Toshihiro Sato, Tokyo (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Jul. 5, 2022, as Appl. No. 17/857,254.
Application 17/857,254 is a continuation of application No. 16/904,898, filed on Jun. 18, 2020, granted, now 11,387,304.
Application 16/904,898 is a continuation of application No. 16/460,026, filed on Jul. 2, 2019, granted, now 10,720,482, issued on Jul. 21, 2020.
Application 16/460,026 is a continuation of application No. 16/175,971, filed on Oct. 31, 2018, granted, now 10,388,711, issued on Aug. 20, 2019.
Application 16/175,971 is a continuation of application No. 15/852,424, filed on Dec. 22, 2017, granted, now 10,147,778, issued on Dec. 4, 2018.
Application 15/852,424 is a continuation of application No. 14/950,897, filed on Nov. 24, 2015, granted, now 9,887,253, issued on Feb. 6, 2018.
Application 14/950,897 is a continuation in part of application No. 14/602,909, filed on Jan. 22, 2015, granted, now 9,806,139, issued on Oct. 31, 2017.
Claims priority of application No. 2014-012823 (JP), filed on Jan. 27, 2014.
Prior Publication US 2022/0336559 A1, Oct. 20, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/1213 (2023.02) [H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01); H01L 29/24 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/78675 (2013.01); H01L 29/7869 (2013.01); H10K 59/1216 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A display device comprising:
a pixel;
a first insulation layer; and
a second insulation layer,
wherein the pixel comprises:
a first poly crystalline silicon layer with a first channel portion which are located at a same layer;
a second poly crystalline silicon layer;
a first transistor with the first channel portion and a first gate electrode portion;
a second transistor with a second channel portion and a second gate electrode portion;
a first metal electrode including the second gate electrode portion; and
a second metal electrode;
the first insulation layer is on the first poly crystalline silicon layer and the second poly crystalline silicon layer,
the first gate electrode portion and the second channel portion are on the first insulation layer,
the second insulation layer is on the first gate electrode portion and the second channel portion,
the first metal electrode is on the second insulation layer, and
the second metal electrode is above the first metal electrode and overlaps the first poly crystalline silicon layer and the second channel portion.