CPC H10B 63/84 (2023.02) [G11C 5/12 (2013.01); G11C 13/0002 (2013.01); H01L 21/823487 (2013.01); H01L 27/1225 (2013.01); H01L 29/4908 (2013.01); H01L 29/66666 (2013.01); H01L 29/66795 (2013.01); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H10B 63/22 (2023.02); H10B 63/24 (2023.02); H10B 63/34 (2023.02); H10N 70/011 (2023.02); H10N 70/245 (2023.02); H10N 70/828 (2023.02); H10N 70/841 (2023.02); H10N 70/883 (2023.02); G11C 11/1659 (2013.01); G11C 11/2259 (2013.01); G11C 11/401 (2013.01); G11C 13/003 (2013.01); G11C 2213/79 (2013.01); H01L 29/78618 (2013.01)] | 16 Claims |
1. A semiconductor device, comprising:
a hybrid transistor configured in a vertical orientation and including:
a gate electrode;
a drain material;
a source material; and
a channel material operatively coupled between the drain material and the source material, wherein the source material and the drain material include a first material and the channel material includes a second, different material, wherein the channel material has a length that is less than a length of the gate electrode.
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