US 12,219,781 B2
Semiconductor structure with embedded memory device
Huang-Kui Chen, Hsinchu (TW); and Guan-Jie Shen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,377.
Application 18/359,377 is a continuation of application No. 16/926,239, filed on Jul. 10, 2020, granted, now 11,793,003.
Prior Publication US 2023/0371281 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 63/00 (2023.01); H01L 23/528 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/34 (2023.02) [H01L 23/528 (2013.01); H10N 70/021 (2023.02); H10N 70/253 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a gate structure over a substrate;
forming a source/drain (S/D) contact structure adjacent to the gate structure;
forming a first layer of resistive material over the S/D contact structure;
forming a second layer of resistive material over the S/D contact structure and embedded in the first layer of resistive material, wherein top surfaces of the first and second layers of resistive material are substantially coplanar;
forming a layer of dielectric material on the first layer of resistive material; and
forming a conductor layer through the layer of dielectric material and in contact with the second layer of resistive material.