| CPC H10B 63/30 (2023.02) [H10B 53/30 (2023.02); H10B 61/22 (2023.02)] | 20 Claims |
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1. A memory device comprising:
a substrate;
a first bit line disposed on the substrate;
a first memory cell disposed on the first bit line;
a first selector layer configured to selectively provide electric power to the first memory cell;
a second bit line disposed on the substrate;
a second memory cell disposed on the second bit line;
a second selector layer configured to selectively provide electric power to the second memory cell;
a dielectric layer disposed on the substrate and in which the first bit line, the second bit line, the first memory cell, the second memory cell, the first selector layer, and the second selector layer are embedded; and
a word line disposed on the dielectric layer and configured to control current flow through the first selector layer and the second selector layer,
wherein the first selector layer and the second selector layer are discrete elements embedded in the dielectric layer, each of the first selector layer and the second selector layer comprising a channel layer comprising amorphous silicon or a semiconducting oxide, and a high-k dielectric layer disposed between the channel layer and the word line.
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