US 12,219,779 B2
Spacer-defined back-end transistor as memory selector
Ken-Ichi Goto, Hsin-Chu (TW); Chung-Te Lin, Tainan (TW); and Mauricio Manfrini, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Apr. 12, 2022, as Appl. No. 17/718,481.
Application 17/718,481 is a continuation of application No. 17/078,583, filed on Oct. 23, 2020, granted, now 11,309,353.
Claims priority of provisional application 63/017,731, filed on Apr. 30, 2020.
Prior Publication US 2022/0246678 A1, Aug. 4, 2022
Int. Cl. H10B 63/00 (2023.01); H10B 61/00 (2023.01)
CPC H10B 61/22 (2023.02) [H10B 63/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate;
a lower interconnect metal structure disposed within an interlayer dielectric (ILD) layer and over the substrate;
a selecting transistor disposed on and contacting the lower interconnect metal structure and within the ILD layer; and
a memory cell disposed over the selecting transistor, the memory cell comprising a bottom electrode electrically connected to the selecting transistor, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.