US 12,219,778 B2
Multi-gate selector switches for memory cells and methods of forming the same
Yong-Jie Wu, Hsinchu (TW); Yen-Chung Ho, Hsinchu (TW); Hui-Hsien Wei, Taoyuan (TW); Chia-Jung Yu, Hsinchu (TW); Pin-Cheng Hsu, Zhubei (TW); Mauricio Manfrini, Zhubei (TW); and Chung-Te Lin, Taiwan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Apr. 14, 2021, as Appl. No. 17/230,664.
Claims priority of provisional application 63/045,329, filed on Jun. 29, 2020.
Prior Publication US 2021/0408117 A1, Dec. 30, 2021
Int. Cl. H10B 61/00 (2023.01); H01L 21/02 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 53/30 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 70/00 (2023.01)
CPC H10B 61/22 (2023.02) [H01L 21/02565 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/78645 (2013.01); H01L 29/7869 (2013.01); H10B 53/30 (2023.02); H10B 63/30 (2023.02); H10N 50/01 (2023.02); H10N 70/063 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A memory structure comprising:
a semiconductor substrate comprising transistors;
a first word line comprising a first top gate electrode and a first bottom gate electrode that are electrically connected and disposed on of the semiconductor substrate;
a second word line comprising a second top gate electrode and a second bottom gate electrode and that are electrically connected and disposed on the semiconductor substrate;
a high-k dielectric layer disposed on the semiconductor substrate, the first bottom gate electrode, and the second bottom gate electrode;
a channel layer disposed on the high-k dielectric layer and under the first top gate electrode and the second top gate electrode, the channel layer comprising an oxide semiconductor thin film transistor material and a drain region that directly contacts the high-k dielectric layer;
a first source electrode and a second source electrode, wherein each of the first source electrode and the second source electrode electrically contacts the channel layer;
a first drain electrode disposed on the drain region of the channel layer, between the first source electrode and the second source electrode;
a memory cell comprising a top electrode and a bottom electrode, wherein a bottom surface of the bottom electrode directly contacts a top surface of the first drain electrode and is coplanar with top surfaces of the first top gate electrode and the second top gate electrode; and
a bit line electrically connected to the top electrode of the memory cell,
wherein the top surface of the first drain electrode is larger than the bottom surface of the bottom electrode,
wherein the first word line, the first source electrode, the first drain electrode, and a first portion of the channel layer form a first thin film transistor (TFT), and the second word line, the second source electrode, the first drain electrode, and a second portion of the channel layer form a second TFT, and
wherein the first TFT and the second TFT are respectively configured to selectively control current flow from the first source electrode and the second source electrode to the memory cell, such that current is simultaneously provided from both the first TFT and the second TFT to the memory cell when selecting the memory cell.