US 12,219,776 B2
Ferroelectric devices including a single crystalline ferroelectric layer and method of making the same
Adarsh Rajashekhar, Santa Clara, CA (US); Raghuveer S. Makala, Campbell, CA (US); and Kartik Sondhi, Milpitas, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Jan. 18, 2022, as Appl. No. 17/578,199.
Prior Publication US 2023/0232634 A1, Jul. 20, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 23/48 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H10B 51/20 (2023.02) [H01L 23/481 (2013.01); H01L 29/2003 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09)] 17 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
an electrically conductive gate electrode embedded within a gate-electrode-level dielectric layer;
a layer stack including a single crystalline III-nitride ferroelectric plate, a gate dielectric layer, and an active region overlying the electrically conductive gate electrode, wherein the active region contains a source region, a drain region, and a channel region extending between the source region and the drain region;
first bonding pads embedded in the gate-electrode-level dielectric layer; and
a support bonded to the gate-electrode-level dielectric layer, wherein the support comprises a semiconductor die containing:
semiconductor devices; and
second bonding pads embedded in dielectric material layers located over the semiconductor devices and bonded to the first bonding pads.