US 12,219,775 B2
Semiconductor structure and method of forming the same
Sheng-Chen Wang, Hsinchu (TW); Meng-Han Lin, Hsinchu (TW); Han-Jong Chia, Hsinchu (TW); and Feng-Cheng Yang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 18, 2022, as Appl. No. 17/577,410.
Claims priority of provisional application 63/230,050, filed on Aug. 5, 2021.
Prior Publication US 2023/0045420 A1, Feb. 9, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H10B 51/10 (2023.01); H10B 51/40 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H10B 51/10 (2023.02); H10B 51/40 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a logic circuit structure;
an interlayer structure, disposed on the logic circuit structure; and
a memory structure, disposed on the interlayer structure, wherein the memory structure comprises:
a word line, extending along a first direction parallel with a top surface of the interlayer structure;
a pair of source line and bit line, extending along a second direction perpendicular to the first direction and perpendicular to the top surface of the interlayer structure; and
an isolation structure, disposed adjacent to the pair of source line and bit line for isolating adjacent memory cells;
a first conductive contact, landing on the word line;
a second conductive contact, penetrating through the isolation structure and the interlayer structure and landing on a conductive feature of the logic circuit structure; and
a conductive line, electrically connected to the first conductive contact and the second conductive contact.