| CPC H10B 43/40 (2023.02) [G11C 16/08 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |
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1. A non-volatile memory chip, comprising:
a cell region that includes
a first surface,
a second surface opposite to the first surface in a second direction,
a cell substrate that includes silicon and is disposed above the first surface,
a cell insulating layer disposed on the cell substrate and below the second surface;
a first cell structure disposed in the cell insulating layer and above the cell substrate in a second direction,
a second cell structure disposed in the cell insulating layer and above the cell substrate in the second direction spaced apart from the first cell structure in a first direction that differs from the second direction; and
a common source line disposed above the cell substrate in the second direction and extending in the first direction;
a peripheral circuit region placed below the first surface of the cell region in the second direction, wherein the peripheral circuit region includes
a peripheral insulating layer below the first surface of the cell region,
a first peripheral circuit disposed in the peripheral insulating layer and connected to the first cell structure,
a second peripheral circuit disposed in the peripheral insulating layer, spaced apart from the first peripheral circuit in the first direction and connected to the second cell structure,
a peripheral substrate disposed below the peripheral insulating layer in the second direction, and
a connection circuit placed in the peripheral substrate between the first and second peripheral circuits;
a through via between the first and second cell structures and that extends from the second surface of the cell region and penetrates through the cell insulating layer, the cell substrate, and the peripheral insulating layer to the connection circuit in the peripheral substrate;
a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and
a chip pad connected to the redistribution layer,
wherein the cell insulating layer and the peripheral insulating layers are spaced apart in the second direction and separated from each other by the cell substrate.
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