US 12,219,773 B2
Embedded pad structures of three-dimensional memory devices and fabrication methods thereof
Jun Chen, Hubei (CN); Zhiliang Xia, Hubei (CN); and Li Hong Xiao, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Dec. 11, 2020, as Appl. No. 17/119,711.
Application 17/119,711 is a division of application No. 16/163,274, filed on Oct. 17, 2018, granted, now 10,930,661.
Application 16/163,274 is a continuation of application No. PCT/CN2018/100852, filed on Aug. 16, 2018.
Prior Publication US 2021/0134824 A1, May 6, 2021
Int. Cl. H10B 43/40 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/40 (2023.02) [H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A method for forming a 3D memory device, comprising:
forming an array device semiconductor structure comprising:
an alternating conductor/dielectric stack disposed on a semiconductor layer, and
an array interconnect layer disposed on the alternating conductor/dielectric stack and including at least one first interconnect structure;
forming a peripheral device semiconductor structure comprising:
at least one peripheral device disposed on a substrate, and
a peripheral interconnect layer disposed on the at least one peripheral device and including at least one second interconnect structure and at least one pad, the at least one pad being electrically connected with the at least one peripheral device through the at least one second interconnect structure;
bonding the array interconnect layer to the peripheral interconnect layer, such that the at least one first interconnect structure is joined with the at least one second interconnect structure; and
forming a pad opening to expose a surface of the at least one pad, wherein the pad opening is disposed so as to penetrate through a section of the alternating conductor/dielectric stack, wherein the pad opening penetrates through the semiconductor layer prior to penetrating through the section of the alternating conductor/dielectric stack.