US 12,219,770 B2
Integrated chip with a gate structure disposed within a trench
Yong-Sheng Huang, Taipei (TW); and Ming Chyi Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 15, 2023, as Appl. No. 18/335,168.
Application 18/335,168 is a division of application No. 17/459,184, filed on Aug. 27, 2021, granted, now 11,723,207.
Prior Publication US 2023/0345728 A1, Oct. 26, 2023
Int. Cl. H10B 43/30 (2023.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H10B 41/30 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/30 (2023.02) [H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H10B 41/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a substrate comprising a first pair of opposing sidewalls that define a trench, wherein the trench extends into a front-side surface of the substrate;
a first source/drain region disposed along the front-side surface of the substrate;
a second source/drain region disposed along the front-side surface of the substrate; and
a gate structure disposed within the trench and arranged laterally between the first source/drain region and the second source/drain region, wherein the gate structure fills the trench and extends along the first pair of opposing sidewalls to an upper surface of the substrate, wherein a bottom surface of the gate structure is disposed below a bottom of the first source/drain region, wherein the gate structure comprises a first gate, a second gate adjacent to the first gate, and a dielectric structure, wherein the dielectric structure continuously laterally extends from an outer sidewall of the first gate to an outer sidewall of the second gate.