US 12,219,768 B2
Three-dimensional semiconductor memory devices
Younghwan Son, Hwaseong-si (KR); and Jeehoon Han, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 22, 2024, as Appl. No. 18/613,389.
Application 18/613,389 is a continuation of application No. 17/838,644, filed on Jun. 13, 2022, granted, now 11,968,836.
Application 17/838,644 is a continuation of application No. 16/528,724, filed on Aug. 1, 2019, granted, now 11,404,429, issued on Aug. 2, 2022.
Claims priority of application No. 10-2018-0167569 (KR), filed on Dec. 21, 2018.
Prior Publication US 2024/0237353 A1, Jul. 11, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01); H10B 43/30 (2023.01); H10B 51/20 (2023.01); H10K 19/00 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/41741 (2013.01); H01L 29/42344 (2013.01); H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10B 43/30 (2023.02); H10B 51/20 (2023.02); H10K 19/201 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) semiconductor memory device comprising:
a substrate;
an electrode structure on a first region of the substrate, the electrode structure comprising gate electrodes stacked in a first direction that is perpendicular to a top surface of the substrate;
a first source conductive pattern between the first region of the substrate and the electrode structure;
a lower sacrificial pattern on a second region of the substrate;
an insulating layer between the second region of the substrate and the lower sacrificial pattern;
a buffer insulating layer on the lower sacrificial pattern;
a vertical semiconductor pattern that penetrates the electrode structure and the first source conductive pattern on the first region of the substrate; and
a dummy vertical pattern that penetrates the buffer insulating layer, the lower sacrificial pattern, and the insulating layer on the second region of the substrate,
wherein each of the buffer insulating layer and the insulating layer includes an oxide layer.