US 12,219,766 B2
Non-volatile memory device including a contour of an insulation film, located below a vertically oriented embedded body, having expanded portion corresponding to the second semicondutor portion of the lower structure
Masaki Tsuji, Yokkaichi (JP); and Yoshiaki Fukuzumi, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 9, 2023, as Appl. No. 18/446,579.
Application 18/446,579 is a continuation of application No. 17/942,249, filed on Sep. 12, 2022, granted, now 11,765,904.
Application 17/942,249 is a continuation of application No. 16/940,472, filed on Jul. 28, 2020, granted, now 11,482,537, issued on Oct. 25, 2022.
Application 16/940,472 is a continuation of application No. 16/360,102, filed on Mar. 21, 2019, granted, now 10,763,279, issued on Sep. 1, 2020.
Application 16/360,102 is a continuation of application No. 15/995,407, filed on Jun. 1, 2018, granted, now 10,283,525, issued on May 7, 2019.
Application 15/995,407 is a continuation of application No. 15/679,301, filed on Aug. 17, 2017, granted, now 10,043,821, issued on Aug. 7, 2018.
Application 15/679,301 is a continuation of application No. 14/643,056, filed on Mar. 10, 2015, granted, now 9,773,803, issued on Sep. 26, 2017.
Claims priority of provisional application 62/047,350, filed on Sep. 8, 2014.
Prior Publication US 2023/0389319 A1, Nov. 30, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 41/42 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 51/20 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/66666 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 41/42 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 51/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device comprising:
a substrate;
an interlayer insulating film provided above the substrate;
a lower structure including first to third semiconductor portions, a first semiconductor portion being provided above the interlayer insulating film, a second semiconductor portion being provided above the first semiconductor portion, and a third semiconductor portion being provided above the second semiconductor portion;
an upper structure including a first interconnection;
electrodes provided between the lower structure and the upper structure, the electrodes being arranged in a first direction orthogonal to a surface of the substrate to constitute a stacked body and functioning plural control gates for plural memory cells;
at least one semiconductor body extending through the electrodes in the first direction and including a first portion on one side and a second portion on the other side in the first direction of the semiconductor body, the first portion being electrically connected to the first interconnection and the second portion being connected to the second semiconductor portion;
an embedded body provided in a slit extending through the electrodes in the first direction and in a second direction orthogonal to the first direction, the embedded body dividing the stacked body into plural portions in a third direction orthogonal to the first direction and the second direction; and
an insulation film provided in the lower structure below the embedded body, a contour of the insulation film in a cross section along the first direction and the third direction including an expanded portion in the third direction at a first level corresponding to the second semiconductor portion in the first direction.