US 12,219,765 B2
Three dimensional memory and methods of forming the same
Sanh D. Tang, Boise, ID (US); and John K. Zahurak, Eagle, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 13, 2023, as Appl. No. 18/209,173.
Application 14/041,928 is a division of application No. 12/825,211, filed on Jun. 28, 2010, granted, now 8,803,214.
Application 18/209,173 is a continuation of application No. 17/129,146, filed on Dec. 21, 2020, granted, now 11,700,730.
Application 17/129,146 is a continuation of application No. 16/716,177, filed on Dec. 16, 2019, granted, now 10,872,903.
Application 16/716,177 is a continuation of application No. 16/125,242, filed on Sep. 7, 2018, granted, now 10,510,769.
Application 16/125,242 is a continuation of application No. 15/722,580, filed on Oct. 2, 2017, granted, now 10,090,324.
Application 15/722,580 is a continuation of application No. 15/188,273, filed on Jun. 21, 2016, granted, now 9,780,115.
Application 15/188,273 is a continuation of application No. 14/041,928, filed on Sep. 30, 2013, granted, now 9,379,005.
Prior Publication US 2023/0413559 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/06 (2006.01); G11C 13/00 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 41/10 (2023.01); H10B 41/20 (2023.01); H10B 41/27 (2023.01); H10B 41/50 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/50 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 21/76838 (2013.01); H01L 23/528 (2013.01); H01L 27/0688 (2013.01); H01L 29/40114 (2019.08); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 41/27 (2023.02); H10B 41/50 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/50 (2023.02); H10B 63/34 (2023.02); H10B 63/845 (2023.02); G11C 2213/71 (2013.01); H10N 70/231 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
conductive regions formed over a substrate;
memory cell strings, each of the memory cell strings formed over a respective conductive region of the conductive regions;
a first control gate formed in a first device level, the memory cell strings including a memory cell string, the memory cell string including a first memory cell having a memory element formed in a cavity of the first control gate;
a second control gate formed in a second device level, the memory cell string including a second memory cell having a memory element formed in a cavity of the second control gate; and
a polysilicon material extending between the first memory cell and the second memory cell and coupled to a conductive region of the conductive regions.