CPC H10B 43/27 (2023.02) [G11C 16/0483 (2013.01)] | 8 Claims |
1. A method of manufacturing a non-volatile memory device, the method comprising:
forming a stack structure on the semiconductor substrate with a source line region;
forming a slit through the stack structure;
forming a sealing layer on an inner wall of the slit;
forming a source liner including a conductive layer on a surface of the sealing layer and a bottom surface of the slit to contact the source line region with the source liner;
forming a gap-filling layer including an insulating material in the slit; and
forming a source contact pattern on the gap-filing layer in the slit.
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