US 12,219,763 B2
Integrated circuit device
Jisung Cheon, Ansan-si (KR); Byunggon Park, Seoul (KR); Joowon Park, Seoul (KR); Sangjun Hong, Hwaseong-si (KR); and Jinsoo Lim, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 13, 2022, as Appl. No. 17/744,092.
Application 17/744,092 is a continuation of application No. 16/710,402, filed on Dec. 11, 2019, granted, now 11,335,695.
Claims priority of application No. 10-2019-0078340 (KR), filed on Jun. 28, 2019.
Prior Publication US 2022/0271056 A1, Aug. 25, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a substrate having a cell region and an interconnection region;
a first stacked structure including a plurality of first insulating layers and a plurality of first word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region;
a second stacked structure including a plurality of second insulating layers and a plurality of second word line structures that are alternately stacked one by one on the first stacked structure in the cell region and the interconnection region;
a first protective insulating layer disposed between and in contact with the first stacked structure and the second stacked structure; and
a second protective insulating layer on the second stacked structure,
wherein:
the first stacked structure and the first protective insulating layer have a first cell channel hole penetrating through the first stacked structure and the first protective insulating layer in the cell region, and at least one first dummy channel hole penetrating through the first stacked structure and the first protective insulating layer in the interconnection region,
the second stacked structure and the second protective insulating layer have a second cell channel hole that is communicatively connected to the first cell channel hole in the cell region, and at least one second dummy channel hole communicatively connected to the at least one first dummy channel hole in the interconnection region,
each of the second cell channel hole and the at least one second dummy channel hole penetrating through the second stacked structure and the second protective insulating layer,
a first width of the first cell channel hole at a level of a top surface of the first protective insulating layer is equal to or less than a second width of the first cell channel hole at a level of a bottom surface of the first protective insulating layer, and
a third width of the at least one first dummy channel hole at the level of the top surface of the first protective insulating layer is greater than a fourth width of the at least one first dummy channel hole at the level of the bottom surface of the first protective insulating layer and a ninth width of the at least one first dummy channel hole at the level above the top surface of the first protective insulating layer in which the second stacked structure contacts the first protective insulating layer.