US 12,219,762 B2
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
John D. Hopkins, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 7, 2022, as Appl. No. 17/571,216.
Application 17/571,216 is a division of application No. 15/930,222, filed on May 12, 2020, granted, now 11,257,839.
Prior Publication US 2022/0130859 A1, Apr. 28, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/32134 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 27 Claims
OG exemplary drawing
 
16. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising n-type conductively-doped polysilicon having a primary n-type conductivity-producing dopant therein;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, a lowest of the conductive tiers comprising n-type conductively-doped polysilicon against directly the n-type conductively-doped polysilicon of the conductor tier and directly against a sidewall of channel material of the channel-material strings in the lowest conductive tier;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising insulating material; and
at least an uppermost portion of the n-type conductively-doped polysilicon in the conductor tier comprising a secondary dopant of different composition from that of the primary dopant.