US 12,219,761 B2
Memory device and manufacturing method of the memory device
Won Geun Choi, Icheon-si Gyeonggi-do (KR); Jung Shik Jang, Icheon-si Gyeonggi-do (KR); Jang Won Kim, Icheon-si Gyeonggi-do (KR); and Mi Seong Park, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Aug. 11, 2021, as Appl. No. 17/399,892.
Claims priority of application No. 10-2021-0024839 (KR), filed on Feb. 24, 2021.
Prior Publication US 2022/0271055 A1, Aug. 25, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 63/00 (2023.01); H10B 41/20 (2023.01); H10B 99/00 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 63/34 (2023.02); H10B 41/20 (2023.02); H10B 99/00 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first gate stack structure and a second gate stack structure; and
a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other,
wherein the slit includes a plurality of first holes extending in a vertical direction, and side portions of the plurality of first holes are connected to side portions of neighboring first holes.