US 12,219,758 B2
Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies
Kamal M. Karda, Boise, ID (US); Haitao Liu, Boise, ID (US); Durai Vishak Nirmal Ramaswamy, Boise, ID (US); Yunfei Gao, Boise, ID (US); Sanh D. Tang, Meridian, ID (US); and Deepak Chandra Pandey, Uttarakhand (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 31, 2024, as Appl. No. 18/428,325.
Application 18/428,325 is a division of application No. 17/734,410, filed on May 2, 2022, granted, now 11,910,597.
Application 17/734,410 is a division of application No. 16/810,009, filed on Mar. 5, 2020, granted, now 11,348,932, issued on May 31, 2022.
Claims priority of provisional application 62/814,689, filed on Mar. 6, 2019.
Prior Publication US 2024/0172432 A1, May 23, 2024
Int. Cl. H10B 41/27 (2023.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 5/025 (2013.01); G11C 5/06 (2013.01); H10B 43/27 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method of forming an integrated assembly, comprising:
forming a stack comprising, in ascending order, a first semiconductor material, an insulative material, a digit line material, and a second semiconductor material; the first semiconductor material being either p-type doped or n-type doped, and the second semiconductor material being the other of p-type doped and n-type doped;
patterning the insulative material, the digit line material, and the second semiconductor material into rails extending along a first direction; the rails being spaced from one another by gaps; regions of the first semiconductor material being exposed along bottom peripheries of the gaps; the rails having sidewalls along the gaps; the patterned digit line material within the rails being digit lines;
forming first insulative spacers along the sidewalls of the rails;
forming semiconductor extensions along the first insulative spacers; the semiconductor extensions and the first insulative spacers narrowing the gaps;
forming second insulative spacers within the narrowed gaps;
forming a planarized surface extending across the rails, the first insulative spacers, the semiconductor extensions and the second insulative spacers;
forming third semiconductor material over and directly against the planarized surface;
forming slits extending through the third semiconductor material to the second insulative spacers; the slits extending linearly along the first direction;
forming insulative panels within the slits;
forming trenches extending through the third semiconductor material and the insulative panels; the trenches extending along a second direction which crosses the first direction; the trenches patterning the third semiconductor material into pillars comprising transistor body regions; the second semiconductor material comprising first source/drain regions under the transistor body regions;
forming gate dielectric material along sidewalls of the transistor body regions;
forming wordlines along the gate dielectric material; the wordlines extending along the second direction;
forming second source/drain regions within upper regions of the pillars;
forming storage elements coupled with the second source/drain regions;
wherein the first source/drain regions, the second source/drain regions and the transistor body regions are together incorporated into access transistors;
wherein the access transistors and the storage elements are incorporated into memory cells of a memory array; and
wherein the semiconductor extensions are configured to drain excess carriers from the transistor body regions to the first semiconductor material during operation of the memory cells.