US 12,219,757 B2
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
John D. Hopkins, Meridian, ID (US); and Nancy M. Lomeli, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 9, 2022, as Appl. No. 17/836,357.
Application 17/836,357 is a division of application No. 15/931,299, filed on May 13, 2020, granted, now 11,387,243.
Prior Publication US 2022/0302154 A1, Sep. 22, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 41/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, channel-material-string structures of memory cells extending through the insulative tiers and the conductive tiers channel material of the channel-material-string structures directly electrically coupling with conductor material of the conductor tier; and
the channel-material-string structures individually comprising an upper portion above and joined with a lower portion between the lowest and the next lowest of the conductive tiers, individual of the channel-material-string structures comprising two and only two external jog surfaces between the lowest and the next lowest of the conductive tiers in a vertical cross-section where the upper and lower portions join, one of the two external jog surfaces being horizontal, the other of the two external jog surfaces not being horizontal.