US 12,219,755 B2
Anti-fuse device and method
Min-Shin Wu, Hsinchu (TW); Meng-Sheng Chang, Hsinchu (TW); Shao-Yu Chou, Hsinchu (TW); and Yao-Jen Yang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 19, 2023, as Appl. No. 18/156,625.
Application 18/156,625 is a continuation of application No. 17/317,162, filed on May 11, 2021, granted, now 11,569,249.
Application 17/317,162 is a continuation of application No. 16/460,266, filed on Jul. 2, 2019, granted, now 11,031,407, issued on Jun. 8, 2021.
Prior Publication US 2023/0157009 A1, May 18, 2023
Int. Cl. G11C 17/00 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10B 20/20 (2023.01)
CPC H10B 20/20 (2023.02) [G11C 17/16 (2013.01); G11C 17/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
an active area positioned in a substrate;
first and second contact structures overlying and electrically connected to the active area;
a conductive element overlying and electrically connected to each of the first and second contact structures;
an anti-fuse transistor device comprising a dielectric layer between a gate structure and the active area;
a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure; and
a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.