US 12,219,752 B2
Method of manufacturing semiconductor structure and semiconductor structure
Cheng Chen, Hefei (CN); Hai-Han Hung, Hefei (CN); Chun-Chieh Huang, Hefei (CN); and Xiaoling Wang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 24, 2022, as Appl. No. 17/648,725.
Application 17/648,725 is a continuation of application No. PCT/CN2021/121011, filed on Sep. 27, 2021.
Claims priority of application No. 202110961599.5 (CN), filed on Aug. 20, 2021.
Prior Publication US 2023/0056308 A1, Feb. 23, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/053 (2023.02); H10B 12/34 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a base, and forming a bit line contact region on the base, wherein a first groove is provided in the bit line contact region;
forming a first bit line contact layer in the first groove, wherein the first bit line contact layer extends to an outside of the first groove and covers the base, and the first bit line contact layer in the first groove defines a second groove;
forming a diffusion layer in the second groove, wherein the diffusion layer extends to an outside of the second groove and covers the first bit line contact layer, and the diffusion layer in the second groove defines a third groove;
forming a second bit line contact layer in the third groove, wherein the second bit line contact layer extends to an outside of third groove and covers the diffusion layer, and a gap is provided in the second bit line contact layer in the third groove; and
processing the diffusion layer to enable ions in the diffusion layer to diffuse into the first bit line contact layer and the second bit line contact layer, and fill up the gap.