| CPC H10B 12/20 (2023.02) [G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); H01L 29/24 (2013.01); H10B 12/50 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02)] | 20 Claims |

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1. An apparatus comprising:
a data line;
a conductive region;
a memory cell including a first transistor and a second transistor, the first transistor including a charge storage structure, and a first channel region coupled to the data line and the conductive region, the second transistor including a second channel region coupled to the data line and the charge storage structure;
a first driver to turn on the first transistor during an operation of reading information from the memory cell, and to turn off the first transistor during an operation of storing information in the memory cell; and
a second driver to turn off the second transistor during the operation of reading information from the memory cell, and to turn on the second transistor during the operation of storing information in the memory cell.
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