US 12,219,749 B2
Method of manufacturing semiconductor device structure having a channel layer with different roughness
Szu-Yao Chang, New Taipei (TW); and Chung-Lin Huang, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Mar. 4, 2022, as Appl. No. 17/653,629.
Prior Publication US 2023/0284431 A1, Sep. 7, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 29/66 (2006.01)
CPC H10B 12/05 (2023.02) [H01L 29/66666 (2013.01); H10B 12/30 (2023.02); H10B 12/488 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device structure, comprising:
forming a first word line extending along a first direction;
forming a second word line extending along the first direction;
forming a gate dielectric structure on a first sidewall of the first word line and on a second sidewall of the second word line;
forming a channel layer on a first sidewall of the gate dielectric structure; and
forming a bit line on the channel layer and extending along a second direction substantially perpendicular to the first direction,
wherein the channel layer has a first sidewall extending along the first direction and a second sidewall extending along the second direction, the first sidewall of the channel layer has a first roughness, and the second sidewall of the channel layer has a second roughness greater than the first roughness of the channel layer.