US 12,219,748 B2
Semiconductor device including a dielectric layer between a source/drain region and a substrate
Kam-Tou Sio, Hsinchu (TW); and Yi-Hsun Chiu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/366,733.
Application 18/366,733 is a continuation of application No. 17/552,500, filed on Dec. 16, 2021, granted, now 11,765,878.
Application 17/552,500 is a continuation of application No. 15/931,658, filed on May 14, 2020, granted, now 11,239,244, issued on Feb. 1, 2022.
Claims priority of provisional application 62/867,315, filed on Jun. 27, 2019.
Prior Publication US 2023/0389259 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 10/00 (2023.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H10B 10/125 (2023.02) [H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor above a substrate and including:
a first source/drain region;
a layer between the first source/drain region and the substrate, wherein the layer is made of a dielectric material;
a second source/drain region in contact with the substrate; and
a channel region in contact with the substrate.