US 12,219,747 B2
Memory active region layout for improving memory performance
Chia-Hao Pao, Kaohsiung (TW); Chih-Chuan Yang, Hsinchu (TW); Shih-Hao Lin, Hsinchu (TW); Chih-Hsuan Chen, Hsinchu (TW); Kian-Long Lim, Hsinchu (TW); Chao-Yuan Chang, New Taipei (TW); Feng-Ming Chang, Hsinchu County (TW); Lien Jung Hung, Taipei (TW); and Ping-Wei Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 12, 2021, as Appl. No. 17/401,151.
Prior Publication US 2023/0046028 A1, Feb. 16, 2023
Int. Cl. H10B 10/00 (2023.01); G06F 30/392 (2020.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H10B 10/125 (2023.02) [G06F 30/392 (2020.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell structure comprising:
a first pull-down (PD) gate-all-around (GAA) transistor, a second PD GAA transistor, a first pass-gate (PG) GAA transistor, and a second PG GAA transistor having a shared active semiconductor region, wherein:
the shared active semiconductor region extends along a first direction, the first PD GAA transistor and the first PG GAA transistor belong to a first memory cell, and the second PD GAA transistor and the second PG GAA transistor belong to a second memory cell adjacent to the first memory cell;
the shared active semiconductor region has a PG active portion that corresponds with the first PG GAA transistor and the second PG GAA transistor and a PD active portion adjacent to the PG active portion that corresponds with the first PD GAA transistor and the second PD GAA transistor;
the first PD GAA transistor and the first PG GAA transistor each have a first channel length and the second PD GAA transistor and the second PG GAA transistor each have a second channel length, wherein the first channel length and the second channel length are along the first direction;
the PG active portion has a width W1 along a second direction and the PD active portion has a width W1′ along the second direction, wherein the second direction is perpendicular to the first direction;
the width W1′ is enlarged with respect to the width W1 by an enlargement width to provide the first PD GAA transistor and the second PD GAA transistor with a first channel width along the second direction and a first threshold voltage and the first PG GAA transistor and the second PG GAA transistor with a second channel width along the second direction and a second threshold voltage;
the first channel width is greater than the second channel width and the first threshold voltage is less than the second threshold voltage;
the PD active portion of the shared active semiconductor region has a first extension portion having a width W2 and a second extension portion having a width W3; and
the PD active portion of the shared active semiconductor region extends beyond a first sidewall of the PG active portion of the shared active semiconductor region along the second direction by the width W2 and beyond a second sidewall of the PG active portion of the shared active semiconductor region along the second direction by the width W3, wherein the width W1 is between the first sidewall of the PG active portion and the second sidewall of the PG active portion and the width W1′ is a sum of the width W1, the width W2, and the width W3.