US 12,219,709 B2
Forming trench in IC chip through multiple trench formation and deposition processes
Kao-Chih Liu, Changhua County (TW); Wenmin Hsu, Hsinchu (TW); Yu-Ting Lin, Hsin-Chu (TW); Chia Hong Lin, Hsinchu County (TW); and ChienYi Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Mar. 28, 2023, as Appl. No. 18/191,787.
Claims priority of provisional application 63/393,556, filed on Jul. 29, 2022.
Claims priority of provisional application 63/409,045, filed on Sep. 22, 2022.
Prior Publication US 2024/0040701 A1, Feb. 1, 2024
Int. Cl. H05K 1/18 (2006.01); G01R 31/28 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01)
CPC H05K 1/18 (2013.01) [G01R 31/2896 (2013.01); H01L 23/5226 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H05K 2201/09036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip assembly, comprising:
an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components, wherein the first structure is disposed over a first side of the first substrate, and wherein the second structure is disposed over a second side of the first substrate opposite the first side;
a second substrate bonded to the IC die through the second side; and
a trench that extends through the second substrate and through the second structure of the IC die, wherein sidewalls of the trench are defined at least in part by one or more protective layers.