US 12,219,632 B2
Method of multi-link power save indication
Minyoung Park, San Ramon, CA (US); Laurent Cariou, Portland, OR (US); Po-Kai Huang, San Jose, CA (US); and Alexander Min, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 14, 2020, as Appl. No. 17/121,355.
Prior Publication US 2021/0100053 A1, Apr. 1, 2021
Int. Cl. H04W 76/00 (2018.01); H04L 1/00 (2006.01); H04L 1/1607 (2023.01); H04W 52/02 (2009.01); H04W 76/15 (2018.01)
CPC H04W 76/15 (2018.02) [H04L 1/0007 (2013.01); H04L 1/1614 (2013.01); H04W 52/0206 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A device, the device comprising processing circuitry coupled to storage, the processing circuitry configured to:
establish two or more links with a non-access point (AP) multi-link device (MLD);
connect a first AP of the device to a first station device (STA) of the non-AP MLD using a first link;
connect a second AP of the device to a second STA of the non-AP MLD using a second link;
use a link bitmap field included in a frame, wherein the link bitmap field comprises a first bit associated with the first STA and a second bit associated with the second STA, wherein a link bitmap size indicates a size of the link bitmap field, and wherein the link bitmap field is configured to be of a variable size based on a value of a bitmap size indicator, with the variable size set to accommodate the number of STAs linked; and
communicate with the non-AP MLD based on the link bitmap.