| CPC H04W 48/02 (2013.01) [H04B 7/0413 (2013.01); H04L 1/0026 (2013.01); H04L 1/0031 (2013.01); H04L 1/1671 (2013.01); H04L 1/1861 (2013.01); H04L 1/1893 (2013.01); H04L 5/001 (2013.01); H04L 5/0023 (2013.01); H04L 5/0055 (2013.01); H04L 5/0057 (2013.01); H04W 28/04 (2013.01); H04W 48/12 (2013.01)] | 6 Claims |

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1. An integrated circuit comprising:
circuitry, which, in operation, controls
transmitting downlink data to a terminal apparatus;
receiving a plurality of transport blocks which are transmitted in a same time period using a same frequency band in a spatial multiplexing scheme, wherein a same acknowledgement information (ACK/NACK) relating to an error detection result of the downlink data is scrambled with different scrambling schemes respectively for the plurality of transport blocks and the respectively scrambled ACK/NACK is multiplexed with data on respective ones of the plurality of transport blocks; and
extracting a combination of the same ACK/NACK scrambled with different scrambling schemes respectively for the plurality of transport blocks from the plurality of transport blocks.
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