US 12,219,284 B2
Solid-state imaging device
Katsuhiko Hanzawa, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLTUIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/001,465
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Jun. 4, 2021, PCT No. PCT/JP2021/021308
§ 371(c)(1), (2) Date Dec. 9, 2022,
PCT Pub. No. WO2021/256291, PCT Pub. Date Dec. 23, 2021.
Claims priority of application No. 2020-105812 (JP), filed on Jun. 19, 2020.
Prior Publication US 2023/0232135 A1, Jul. 20, 2023
Int. Cl. H04N 25/78 (2023.01); H04N 25/75 (2023.01); H04N 25/76 (2023.01); H04N 25/77 (2023.01)
CPC H04N 25/78 (2023.01) [H04N 25/75 (2023.01); H04N 25/76 (2023.01); H04N 25/77 (2023.01)] 17 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a plurality of pixel regions, wherein
each of the plurality of pixel regions includes:
a first photoelectric conversion unit;
a second photoelectric conversion unit that overlaps the first photoelectric conversion unit;
a first readout circuit electrically connected to the first photoelectric conversion unit, wherein the first readout circuit is configured to read out a current from the first photoelectric conversion unit; and
a second readout circuit electrically connected to the second photoelectric conversion unit, wherein
the second readout circuit is configured to read out a first voltage converted from a first charge of the second photoelectric conversion unit, and
the second readout circuit is a circuit of a high-impedance input.