US 12,219,282 B2
Image sensor, method of controlling image sensor, and electronic device
Atsumi Niwa, Kanagawa (JP); Tomonori Yamashita, Kanagawa (JP); Takashi Moue, Kanagawa (JP); and Yosuke Ueno, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on Apr. 7, 2023, as Appl. No. 18/132,346.
Application 18/132,346 is a continuation of application No. 17/326,242, filed on May 20, 2021.
Application 17/326,242 is a continuation of application No. 16/488,734, granted, now 11,039,098, previously published as PCT/JP2018/005650, filed on Feb. 19, 2018.
Claims priority of application No. 2017-039337 (JP), filed on Mar. 2, 2017; and application No. 2017-117453 (JP), filed on Jun. 15, 2017.
Prior Publication US 2023/0247329 A1, Aug. 3, 2023
Int. Cl. H04N 25/772 (2023.01); H03K 5/24 (2006.01); H03M 1/34 (2006.01); H04N 25/75 (2023.01)
CPC H04N 25/772 (2023.01) [H03K 5/2481 (2013.01); H03M 1/34 (2013.01); H04N 25/75 (2023.01)] 13 Claims
OG exemplary drawing
 
1. A light detecting device comprising:
a pixel configured to generate a pixel signal; and
a comparator comprising:
a first capacitor configured to receive the pixel signal;
a second capacitor configured to receive a reference signal;
a first node coupled to the first capacitor and the second capacitor; and
a single type amplifier including:
a first transistor having a gate coupled to the first node;
a second transistor disposed between a first line supplied with a first voltage and the first transistor; and
a third transistor disposed between the first transistor and the second transistor,
wherein the first transistor is coupled between the second transistor and a second line supplied with a second voltage different from the first voltage,
wherein a polarity of the first transistor is opposite to a polarity of the second transistor,
wherein a gate of the second transistor is configured to receive a first bias voltage,
wherein a gate of the third transistor is coupled to the first line and the gate of the second transistor is coupled to a second line,
wherein a third capacitor is coupled to the gate of the second transistor and the first line, and
wherein the gate of the second transistor is configured to receive the first bias voltage via a third switch.