| CPC H04N 25/772 (2023.01) [H03M 1/141 (2013.01); H03M 1/56 (2013.01); H04N 25/60 (2023.01); H04N 25/771 (2023.01)] | 16 Claims |
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1. An image sensor comprising:
a pixel array disposed in a Bayer pattern and including pixels which respectively generate an electrical charge according to incident light; and
an analog logic configured to:
convert an analog signal output from at least one pixel among the pixels into a first digital code consisting of N-bits using analog-to-digital conversion, where N is a positive integer;
receive a control signal;
generate a second digital code consisting of N-k bits by eliminating k low-order bits of the first digital code in response to the control signal, where k is an integer less than N and greater than zero, wherein the N-k bits of the second digital code are the same as N-k high-order bits of the first digital code and k is variably controlled by the control signal,
wherein the analog logic includes:
an analog digital converter (ADC) controller configured to generate the control signal in response to a gain adjust signal; and
an analog digital converter (ADC) configured to adjust an analog gain in response to the control signal and amplify the analog signal using the analog gain, wherein the analog logic determines k based on a signal level of the analog signal and a level of the gain adjust signal,
wherein the image sensor further comprises a digital logic configured to receive the second digital code and receive the control signal from the ADC controller, the digital logic including a random bit generator configured to generate k number of random bits based on the control signal, and
wherein the digital logic is configured to combine the second digital code with the k number of random bits to generate a third digital code, the third digital code being represented by the same number of bits as the first digital code.
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