US 12,219,275 B2
Solid imaging device and electronic device
Atsushi Muto, Shizuoka (JP); Shinichirou Etou, Kanagawa (JP); Atsumi Niwa, Kanagawa (JP); and Masafumi Yamashita, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 18/246,821
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Oct. 14, 2021, PCT No. PCT/JP2021/038014
§ 371(c)(1), (2) Date Mar. 27, 2023,
PCT Pub. No. WO2022/091795, PCT Pub. Date May 5, 2022.
Claims priority of application No. 2020-180109 (JP), filed on Oct. 28, 2020.
Prior Publication US 2023/0362503 A1, Nov. 9, 2023
Int. Cl. H04N 25/47 (2023.01); H04N 25/77 (2023.01); H04N 25/78 (2023.01)
CPC H04N 25/47 (2023.01) [H04N 25/77 (2023.01); H04N 25/78 (2023.01)] 15 Claims
OG exemplary drawing
 
1. A solid imaging device including:
a plurality of unit pixels arrayed in a two-dimensional lattice pattern;
an arbiter that arbitrates readout with respect to the plurality of unit pixels; and
a first signal processing circuit that processes a first signal output from each of the unit pixels, wherein
each of the unit pixels includes
a plurality of photoelectric conversion sections arrayed in a two-dimensional lattice pattern, and
a plurality of detection circuits that detects a luminance change in incident light to the photoelectric conversion sections on a basis of a photocurrent flowing out from each of the photoelectric conversion sections and outputs the first signal,
the plurality of photoelectric conversion sections is arranged on a first chip,
at least a part of each of the detection circuits, the arbiter, and the first signal processing circuit are arranged on a second chip stacked on the first chip,
a first region in the first chip in which the plurality of photoelectric conversion sections is arrayed and a second region in the second chip in which at least a part of each of the detection circuits is arrayed are at least partially superimposed in a stacking direction of the first chip and the second chip, and
a logic circuit including the arbiter and the first signal processing circuit is arranged in a third region at least partially adjacent to the second region in the second chip.