US 12,219,247 B2
Imaging device, imaging system, and imaging method
Naoki Kawazu, Kanagawa (JP); Keita Sasaki, Kanagawa (JP); Takumi Oka, Kanagawa (JP); Yuichi Motohashi, Tokyo (JP); and Atsushi Suzuki, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Jun. 20, 2023, as Appl. No. 18/337,651.
Application 18/337,651 is a continuation of application No. 17/735,612, filed on May 3, 2022, granted, now 11,729,496.
Application 17/735,612 is a continuation of application No. 16/970,066, granted, now 11,343,427, previously published as PCT/JP2019/004036, filed on Feb. 5, 2019.
Claims priority of application No. 2018-029771 (JP), filed on Feb. 22, 2018.
Prior Publication US 2023/0336867 A1, Oct. 19, 2023
Int. Cl. H04N 23/65 (2023.01); H04N 23/70 (2023.01); H04N 25/683 (2023.01); H04N 25/75 (2023.01); H04N 25/79 (2023.01)
CPC H04N 23/65 (2023.01) [H04N 23/749 (2023.01); H04N 25/683 (2023.01); H04N 25/75 (2023.01); H04N 25/79 (2023.01)] 14 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a first substrate including a pixel array; and
a second substrate including:
a first terminal region including:
a first pad electrode configured to receive a first voltage, and
a second pad electrode configured to receive a second voltage different from the first voltage, wherein the first voltage is a ground voltage;
a voltage sensor region including a voltage sensor coupled to the first pad electrode and the second pad electrode;
a readout circuit region including an AD converter coupled to the voltage sensor; and
a second terminal region including a third terminal configured to output an error flag based on an output of the AD converter, wherein
the voltage sensor region is between the first terminal region and the readout circuit region in a plan view, and
the second terminal region is on a side opposite to the first terminal region with respect to the readout circuit region in the plan view.