| CPC H04N 19/13 (2014.11) [H04N 19/119 (2014.11); H04N 19/124 (2014.11); H04N 19/176 (2014.11); H04N 19/61 (2014.11)] | 10 Claims |

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1. An apparatus for decoding a video signal, comprising:
a memory configured to store the video signal; and
a processor coupled with the memory,
wherein the processor is configured to:
parse a transform skip flag specifying whether a transform is applied to the current block based on a size of the current block being smaller than a predetermined first size;
obtain an index specifying one of a plurality of transform kernel combinations to be applied to the current block based on the transform skip flag, each transform kernel combination being composed of a transform kernel in a horizontal direction and a transform kernel in a vertical direction; and
generate an inverse transformed transform block of the current block by performing an inverse transform to a residual block based on the transform kernel combination specified by the index,
wherein for obtaining the index, the processor is further configured to:
check a value of an index flag related to parsing the index, based on the transform skip flag being 0; and
derive the index specifying the transform kernel combination as DCT-2 for the transform kernels in the horizontal and vertical directions based on the value of the index flag being 0.
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