US 12,219,057 B2
Implementing trusted executing environments across multiple processor devices
Philip John Rogers, Austin, TX (US); Mark Overby, Snohomish, WA (US); Michael Asbury Woodmansee, Lighthouse Point, FL (US); Vyas Venkataraman, Sharon, MA (US); Naveen Cherukuri, San Jose, CA (US); Gobikrishna Dhanuskodi, Santa Clara, CA (US); Dwayne Frank Swoboda, San Jose, CA (US); Lucien Burton Dunning, Ramsey, NJ (US); Mark Hairgrove, San Jose, CA (US); and Sudeshna Guha, Bangalore (IN)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,110.
Prior Publication US 2023/0094125 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 29/00 (2006.01); G06F 9/455 (2018.01); H04L 9/08 (2006.01); H04L 9/30 (2006.01)
CPC H04L 9/0877 (2013.01) [G06F 9/45558 (2013.01); H04L 9/0841 (2013.01); H04L 9/30 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45587 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A system comprising:
one or more processors coupled with a protected memory region to:
instantiate a virtual machine supported by a processor of the one or more processors; and
execute, using a graphics processing unit (GPU) of the one or more processors, at least a portion of an application associated with the virtual machine by at least:
negotiating, by generating a shared secret based, at least in part, on a private key associated with the GPU, a cryptographic key to encrypt data transmitted between the processor and the GPU; and
causing a compute engine of the GPU to be prevented from writing outside of the protected memory region as a result of the compute engine accessing the protected memory region.