CPC H04L 9/0825 (2013.01) [G06E 3/005 (2013.01); G06Q 20/367 (2013.01); H04L 9/0643 (2013.01); H04L 9/085 (2013.01); H04L 9/0891 (2013.01); G02B 6/12002 (2013.01); G02B 6/12004 (2013.01)] | 20 Claims |
1. A photonic processor, comprising:
a first photonic circuit configured to generate a plurality of new messages based at least in part on a plurality of input messages; and
a second photonic circuit coupled to the first photonic circuit via a set of optical connections, the second photonic circuit configured, during a plurality of operational cycles, to:
receive, from the first photonic circuit via the set of optical connections, the plurality of new messages, and
update a plurality of keys based at least in part on the received plurality of new messages,
wherein the second photonic circuit is further configured to generate at least one hash value based on the plurality of keys generated after the plurality of operational cycles.
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