US 12,219,020 B2
Systems and methods for processing heartbeat packets in switching hardware
Michael Chih-Yen Wang, Vancouver (CA); Victor Shih-Hua Wen, San Jose, CA (US); and Navdeep Bhatia, Sunnyvale, CA (US)
Assigned to Arista Networks, Inc., Santa Clara, CA (US)
Filed by Arista Networks, Inc., Santa Clara, CA (US)
Filed on Jul. 12, 2022, as Appl. No. 17/863,129.
Prior Publication US 2024/0022638 A1, Jan. 18, 2024
Int. Cl. H04L 67/145 (2022.01); H04L 67/62 (2022.01)
CPC H04L 67/145 (2013.01) [H04L 67/62 (2022.05)] 18 Claims
OG exemplary drawing
 
1. A method for performing heartbeat packet detection and processing in a network device, the method comprising:
maintaining, by a switching application specific integrated circuit (ASIC) implementing a heartbeat mechanism in a network device, heartbeat session entries for a plurality of heartbeat sessions, the switching ASIC tracking aging of each of the heartbeat session entries, sweeping the heartbeat session entries to identify expired heartbeat session entries, and providing notification of the expired heartbeat session entries to a central processing unit (CPU) of the network device;
receiving, by the switching ASIC, a first incoming packet;
determining, by the switching ASIC, the first incoming packet is a heartbeat packet;
processing, by the switching ASIC, the heartbeat packet by:
checking one or more flags of the heartbeat packet;
determining that one of a first subset of the one or more flags is set and resetting an aging timer for a corresponding one of the heartbeat session entries, and trapping to the CPU for further processing of the heartbeat packet; and
determining that one of a second subset of the one or more flags is set and trapping to the CPU for further processing of the heartbeat packet without resetting the aging timer for the corresponding one of the heartbeat session entries;
receiving, by the switching ASIC, a second incoming packet;
determining, by the switching ASIC, the second incoming packet is not the heartbeat packet; and
offloading, by the switching ASIC, processing of the second incoming packet to the CPU.