US 12,218,840 B2
Flexible scheme for adding rules to a NIC pipeline
Manasi Deval, Portland, OR (US); Elazar Cohen, Haifa (IL); Shaul Yifrach, Haifa (IL); and Parthasarathy Sarangam, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 16, 2020, as Appl. No. 16/902,371.
Prior Publication US 2020/0314011 A1, Oct. 1, 2020
Int. Cl. H04L 45/7453 (2022.01); H04L 45/00 (2022.01); H04L 45/745 (2022.01); H04L 69/22 (2022.01)
CPC H04L 45/7453 (2013.01) [H04L 45/38 (2013.01); H04L 45/54 (2013.01); H04L 45/74591 (2022.05); H04L 69/22 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A system, comprising:
a processor having a plurality of cores;
memory, coupled to the processor;
software instructions configured to be executed on one or more of the plurality of cores to cause the system to,
implement a plurality of match-action tables in the memory, the match-actions tables configured to store a plurality of match-action entries at respective indexes in each match action table; and
perform a lookup into the plurality of match-action tables using a multi-hash scheme;
a network interface including:
a first port;
a packet processing pipeline; and
an exact match (EM) cache in which a plurality of match-action entries cached from the plurality of match-action tables in memory are stored,
wherein the system is configured to atomically add and remove match-action entries in the EM cache and the plurality of match-action tables.