US 12,218,786 B1
Clock recovery for PAM4 signaling using bin-map
Hemlata Bist, Noida (IN); Rohit Mishra, Noida (IN); Harshit Jaiswal, Agra (IN); and Shubham Agarwal, Gorakhpur (IN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Nov. 21, 2022, as Appl. No. 17/991,747.
Int. Cl. H04L 25/49 (2006.01); H04B 14/02 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01)
CPC H04L 25/4921 (2013.01) [H04B 14/023 (2013.01); H04L 7/0079 (2013.01); H04L 7/0334 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A clock recovery apparatus for multi-level signaling on a single lane communication interface, comprising:
bin-map logic to recover a common clock from each individual clock corresponding to each bit in a multi-bit symbol received on the single lane communication interface using the multi-level signaling.